IIC vs SPI

Nowadays, in the field of low-end digital communication applications, we can see it everywhereThe presence of IIC (Inter Integrated Circuit) and SPI (Serial Peripheral Interface). The reason is that these two communication protocols are very suitable for close range low-speed chip to chip communication. Philips (for IIC) and Motorola (for SPI) have developed these two standard communication protocols based on different backgrounds and market demands.

IIC was developed in 1982 to provide a simpler way to interconnect the CPU and peripheral chips inside televisions. Television is one of the earliest embedded systems, which used memory mapped I/O to interconnect microcontrollers and peripheral devices. To achieve memory mapping, the device must be connected in parallel to the data and address lines of the microcontroller. This method requires a large number of lines and additional address decoding chips when connecting multiple peripherals, which is inconvenient and costly.

In order to save pins and additional logic chips for microcontrollers, make printed circuit boards simpler and more cost-effective, located in the NetherlandsPhilips laboratory has developed the 'Inter Integrated Circuit', IIC or IIC, a bus protocol that uses only two wires to connect all peripheral chips. The initial standard defined a bus speed of 100kbps. After several revisions, mainly 400kbps in 1995 and 3.4Mbps in 1998.

There are indications that,The SPI bus was first introduced in 1979, when Motorola integrated it into their first microcontroller chip based on the 68000 microprocessor. The SPI bus is an external bus (relative to the internal bus) for microcontrollers with four wires. Unlike IIC, SPI does not have a plaintext standard, but rather a factual standard that provides a general abstract description of the implementation of communication operations. Chip manufacturers and driver developers communicate implementation details through data sheets and application notes.

SPI

For experienced digital electronics engineers, usingSPI interconnection between two digital devices is quite intuitive. SPI is a protocol with four signal lines (as shown in the figure):

 

·SCLK: Serial Clock (output from master);

·MOSI; SIMO: Master Output, Slave Input(output from master);

·MISO; SOMI: Master Input, Slave Output(output from slave);

·SS: Slave Select (active low, outputfrom master).

SPI is a single master communication protocol, which means that only one central device in the bus can initiate communication. When the SPI master device wants to read/write to the slave device, it first lowers the SS line corresponding to the slave device (SS is a low level valid), and then starts sending working pulses to the clock line. At the corresponding pulse time, the master device sends the signal to MOSI to achieve "write", and can also sample MISO to achieve "read", as shown in the following figure:

 

SPI has four operating modes - Mode 0, Mode 1, Mode 2, and Mode 3. The difference between them is that they define which edge of the clock pulse to toggle the output signal, which edge to sample the input signal on, and the stable level value of the clock pulse (i.e. whether it is high or low when the clock signal is inactive). Each mode is characterized by a pair of parameters called clock polarity CPOL and clock phase CPHA.

 

The master and slave devices must use the same working parameters——SCLK, CPOL, and CPHA are required to function properly. If there are multiple [slave devices] and they use different operating parameters, then the [master device] must reconfigure these parameters between reading and writing different [slave devices]. The main content of the SPI bus protocol mentioned above. SPI does not specify a maximum transmission rate and does not have an address scheme; SPI also does not specify a communication response mechanism or flow control rules. In fact, SPI [master device] does not even know whether the specified [slave device] exists. These communication controls must be implemented independently outside of the SPI protocol. For example, to connect a command response control decoding chip with SPI, a more advanced communication protocol must be implemented based on SPI. SPI does not care about the electrical characteristics of physical interfaces, such as the standard voltage of signals. Initially, most SPI applications used intermittent clock pulses and transmitted data in bytes, but now there are many variations that implement continuous time pulses and data frames of any length.

IIC

WithUnlike single master devices in SPI, IIC is a bus for multiple master devices. IIC does not have physical chip selection signal lines or arbitration logic circuits, and only uses two signal lines - 'serial data' (SDA) and 'serial clock' (SCL). The IIC protocol stipulates that:

·Firstly, each oneIIC devices all have a unique seven digit device address;

·Secondly, the data frame size is8-bit byte;

·Thirdly, certain data bits in the data (frame) are used to control the start, stop, direction (read/write), and response mechanism of communication.

IIC data transmission rates include standard mode (100 kbps), fast mode (400 kbps), and high-speed mode (3.4 Mbps), while some variants implement low-speed mode (10 kbps) and fast mode (1 Mbps).

In terms of physical implementation,The IIC bus consists of two signal lines and one ground line. Both signal lines are bidirectional transmission, refer to the following diagram. The IIC protocol standard specifies that the device initiating communication is called the master device, and after the master device initiates a communication, all other devices are slave devices.

The IIC communication process is roughly as follows. Firstly, the main device sends a START signal, which is like shouting to all other devices: Please pay attention! Then other devices start listening to the bus to prepare for receiving data. Next, the main device sends a 7-bit device address plus one bit read/write operation data frame. After receiving data, the device compares its address with that of the target device. If the comparison does not match, the device enters a waiting state, waiting for the arrival of the STOP signal; If the comparison matches, the device will send a response signal - ACKNOWLEDGE in response.

When the main device receives a response, it begins to transmit or receive data. The data frame size is8-digit response signal followed by one digit. The master device sends data and the slave device responds; On the contrary, when the main device receives data, it responds. When the data transfer is completed, the main device sends a STOP signal to announce the release of the bus to other devices, and other devices return to their initial state.

 be based onThe physical structure of the IIC bus ensures that the START and STOP signals on the bus are unique. In addition, the IIC bus standard stipulates that data conversion on the SDA line must occur during the low-level period of the SCL line, and during the high-level period of the SCL line, the data on the SDA line must be stable.

In terms of physical implementation,The SCL and SDA lines are both open drain, and a voltage source is applied through a pull-up resistor. When the line is grounded, the line is logic 0, and when the line is released and idle, the line is logic 1. Based on these characteristics, IIC devices only operate the bus by "grounding the line" - outputting logic 0.

The IIC bus design only uses two lines, but elegantly achieves seamless communication between any number of devices, making it perfect. Let's imagine what would happen if two devices were to send messages to both the SCL and SDA lines simultaneously.

be based onThe design of IIC bus ensures that there is no possibility of level conflict on the circuit. If one device sends logic 0 and the others send logic 1, then the line only sees logic 0. That is to say, if there is a level conflict, the one who sends logic 0 is always the "winner".

The physical structure of the bus also allows the master device to read data while writing to the bus. In this way, any device can detect the occurrence of conflicts. When two main devices compete for the bus,The 'winner' is unaware of the occurrence of competition, only the 'loser' discovers the conflict - when it writes a logic 1 but reads 0- and exits the competition.

10 digit device address

whateverIIC devices all have a 7-bit address, theoretically, there can only be 127 different IIC devices in reality. In fact, there are far more types of IIC devices than this limitation, and the probability of IIC devices with the same address appearing on a bus is quite high. To overcome this limitation, many devices use dual addresses -7-bit addresses plus external configuration pins. The IIC standard also anticipates this limitation and proposes a 10 bit address scheme.

The impact of a 10 bit address scheme on the IIC protocol is twofold:

·Firstly, the address frame is two bytes long, whereas it was originally one byte;

·Secondly, the first five most significant bits of the first byte are used as10 digit address identifier, agreed to be "11110".

 

exceptA 10 digit address identifier is provided, and the standard also reserves some address codes for other purposes, as shown in the table below:

 

Clock stretching

stay In IIC communication, the master device determines the clock speed. Because the clock pulse signal is explicitly emitted by the main device. However, when the slave device cannot keep up with the speed of the master device, the slave device needs a mechanism to request the master device to slow down a bit. This mechanism is called clock stretching, and based on the particularity of the I ² C structure, this mechanism is implemented. When the slave device needs to reduce the transmission speed, it can press the clock line to force the master device into a waiting state until the slave device releases the clock line, and communication continues.

High speed mode

In principle, a pull-up resistor is used to set the logic1 will limit the maximum transmission speed of the bus. And speed is one of the limiting factors for bus applications. This also explains why high-speed mode (3.4 Mbps) is being introduced. Before initiating a high-speed mode transmission, the master device must first emit a specific "High Speed Master" signal in low-speed mode (such as fast mode). To shorten the signal cycle and improve bus speed, additional I/O buffers must be used in high-speed mode. In addition, bus arbitration can be blocked in high-speed mode. For more information, please refer to the bus standard document.

IIC vs SPI: Who is the winner?

Let's compare itSome key points of IIC and SPI:

Firstly, the bus topology structure/Signal routing/hardware resource consumption

IIC only requires two signal lines, while standard SPI requires at least four signals. If there are multiple slave devices, more signals are needed. Although some SPI variants only use three wires - SCLK, SS, and bidirectional MISO/MOSI - the SS wire still needs to be paired with the slave device. In addition, if SPI wants to implement a multi master device structure, the bus system requires additional logic and circuits. The only issue with building a system bus using IIC is the limited 7-bit address space, but this problem has been solved by the new standard - using 10 bit addresses. From the first point of view, IIC is a clear big winner.

Secondly, data throughput/Transmission speed

If high-speed data transmission is required in the application, thenSPI is an inevitable choice. Because SPI is full duplex, IIC is not. SPI does not define a speed limit, and typical implementations can typically reach or even exceed 10 Mbps. The highest speeds of IIC are fast mode (1 Mbps) and high-speed mode (3.4 Mbps), and the latter modes require additional I/O buffers, which are not always easy to implement.

Thirdly, elegance

IIC is often referred to as more elegant than SPI. To be fair, we tend to believe that both are equally elegant and robust. The elegance of IIC lies in its feature of implementing multi master device arbitration and device routing with a very lightweight architecture. But for the engineers who use it, understanding the bus structure is more difficult, and the performance of the bus is not high.

The advantage of SPI lies in its intuitive and simple structure, easy implementation, and good scalability. The simplicity of SPI is not enough to call it elegant, because to build a useful communication platform using SPI, specific communication protocol software needs to be built on top of SPI. That is to say, in order to obtain the unique feature of SPI that IIC does not have - high-speed performance, engineers need to put in more effort. In addition, this custom work is completely free, which also explains why SPI does not have an official standard. Both IIC and SPI provide good support for low-speed device communication, but SPI is suitable for data stream applications, while IIC is more suitable for multi master device applications of "byte devices".

Summary

In the digital communication protocol suite,IIC and SPI are often referred to as "small" protocols, which have transmission speeds of hundreds of gigabytes per second compared to buses such as Ethernet, USB, SATA, PCI Express, etc. However, what we cannot forget is the purpose of various buses. The 'big' protocol is used for communication between the entire system outside the system, while the 'small' protocol is used for communication between chips within the system. There is no indication that the 'big' protocol is necessary to replace the 'small' protocol. The existence and popularity of IIC and SPI reflect the philosophy of 'enough is enough'. In response to the beginning of the article, IIC and SPI are so popular that they are essential tools for any embedded engineer.

 
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